1. Field of the Invention
The present invention relates to an ESD protection circuit with high performance.
2. Description of the Prior Art
With the continuous scaling down of VLSI feature size, VLSI circuit manufacturers are making semiconductor devices with thinner gate oxide layers to meet the scale down rule and increase device performance. Therefore, VLSI gate layer thickness is being continuously reduced. The gate oxide thickness in the present technology is approximately 60 angstrom for deep half-micro meter technology. Nordheim-Fowler tunneling current is found at the 7M/cm electric field across gate oxide regions. Thus, a semiconductor MOS device cannot sustain an electric field greater than 7MV/cm across gate oxide regions without being damaged over time. Consequently, the maximum voltage across gate oxide regions of a 60-angstrom thickness MOS transistor without suffering damage over time is 60 xc3x85xc3x977M/cm=4.2V. In practice, the maximum voltage is smaller than 4.2V due to process variables, such as defects.
This low gate oxide thickness will especially cause problems in I/O and ESD protection circuits. For some core elements, for example a microprocessor, feature dimensions and operation speeds are smaller and faster than those of periphery devices, for example an RS232 interface. The power supply and voltage swing needed for core elements are also getting smaller than those needed for periphery circuits. Moreover, the I/O circuits run at a higher voltage than the core circuits. Accordingly, a voltage higher than the supply voltage may be applied to some of the gate oxide regions with uniform thickness, which causes problems in gate oxide reliability.
To avoid the above problems, various kinds of ESD protection circuit have been proposed. An ESD protection circuit is provided in U.S. Pat. No. 5,532,178, which uses an undoped silicon poly gate as an ESD transistor so that the ESD protection transistor can withstand a voltage higher than the supply voltage. However, this results in an Lunstable Vt and a need for additional masks. Another ESD protection circuit is provided in U.S. Pat. No. 5,696,397, which comprises a parasitic MOS transistor, but does not provide for full swing. Moreover, a depletion MOS transistor is used in the ESD protection circuit provided in U.S. Pat. No. 5,495,185, but increases the complexity of process.
FIG.1 is a block diagram showing a traditional ESD protection circuit 10. The ESD protection circuit 10 comprises a pad 11 and two transistors 13, 15. An internal circuit 17 is connected to the ESD protection circuit 10 to be protected from damage by ESD. The transistor 13 has a drain connected to the pad 11 and a gate connected to an input node for a supply voltage Vdd. The transistor 15 has a drain connected to the source of the transistor 13, and a gate and a source both connected to an input node for a supply voltage Vss. However, when ESD occurs and the supply voltage Vdd is not applied, the transistor 13 will be turned off. Thus, the long distance between the drain of the transistor 15 and the source of the transistor 13 will result in an undesirable : gain of the lateral NPN and therefore decrease the ESD capability. In addition, the drain of the transistor 15 will be floating and there will be no net current flowing from the drain to the source of the transistor 15. Therefore, hot electron accelerated avalanche breakdown will never occur in the transistor 15, which will result in a high avalanche voltage and further decrease the ESD capability.
The object of the present invention is to solve the above-mentioned problems and to provide an ESD protection circuit in which a bias voltage resulting from the occurrence of ESD is applied to the gate of the transistor 13 so that the transistor 13 is turned on upon the occurrence ESD.
To achieve the above-mentioned object, the present invention provides an ESD protection circuit for preventing an internal circuit from being damaged by ESD, wherein the internal circuit is connected to a pad. The ESD protection circuit comprises a first transistor, a second transistor and a voltage divider. The first transistor has a drain connected to the pad. The second transistor has a source and a gate both connected to an input node for a supply voltage, and has a drain connected to a source of the first transistor. The voltage divider is connected between the pad and the input node for the supply voltage, and also connected to a gate of the first transistor for providing a bias voltage thereto when ESD occurs.
The present invention also provides an ESD protection circuit for preventing an internal circuit from being damaged by ESD, wherein the internal circuit is connected to a pad. The ESD protection circuit comprises a first transistor, a second transistor and a voltage divider. The first transistor has a drain connected to the pad. The second transistor has a source and a gate both connected to an input node for a supply voltage, and has a drain connected to a source of the first transistor: The voltage divider is connected between the pad and the input node for the supply voltage, and comprises an upper load and a lower load connected in series. The upper load and lower load are also connected to the pad and the input node for the supply voltage respectively. The gate of the first transistor is connected to where the upper load and lower load are connected together for receiving a bias voltage when ESD occurs.
Accordingly, the present invention solves the above-mentioned problems by providing a voltage divider which, upon the occurrence of ESD, provides a bias voltage to the gate of the first transistor and therefore turning on the first transistor, thus maintaining a high ESD capability.